1. Technical Field
The present invention relates to decoding compressed video signals, and more particularly relates to a system and method for scaling an MPEG-2 video decoder.
2. Related Art
The MPEG standards are an evolving set of standards for video and audio compression developed by the Moving Picture Experts Group (MPEG). MPEG-1 was designed for coding progressive video at a transmission rate of about 1.5 million bits per second. It was designed specifically for Video-CD and CD-i media. MPEG-2 was designed for coding interlaced images at transmission rates above 4 million bits per second. The MPEG-2 standard is used for various applications, such as digital television (DTV) broadcasts, digital versatile disk (DVD) technology, and video storage systems.
According to the MPEG-2 standard, an MPEG-2 sequence is divided into a series of GOPs (Group Of Pictures). There are three different types of pictures, with each being essentially a frame of pixels. Each GOP begins with an Intra-coded picture (I picture) followed by an arrangement of forward Predictive-coded pictures (P pictures) and Bi-directionally predictive-coded pictures (B pictures). I pictures are fields or frames coded as a stand-alone still image. P pictures are fields or frames coded relative to the nearest I or P picture, resulting in forward prediction processing. P pictures allow more compression than I pictures through the use of motion compensation, and also serve as a reference for B pictures and future P pictures. B pictures are fields or frames that use the most proximate past and future I and P pictures as a reference, resulting in bi-directional prediction.
As the digital TV market gradually begins to dominate the TV market and other video applications become more desirable, the demand for systems having advanced capabilities for processing MPEG-2 pictures becomes stronger and stronger. The current emerging architecture for processing MPEG-2 data, such as that found in DTV set-top boxes and high end digital TV's, typically utilize a combination of a digital signal processing central processing units (DSPCPU), control processors, coprocessors, and software applications. Unfortunately, even with all these resources, advanced audio/visual processing functions tend to consume more computational power than is often available.
One of the key elements in MPEG-2 processing is the MPEG-2 decoder, which converts a bitstream of compressed MPEG-2 data into pixel images. The main components of a generic MPEG-2 decoder 10 are shown in FIG. 1. There are four functional blocks: a variable length decoder (VLD) 12, an inverse quantization (IQ) system 14, an inverse discrete cosine transform system (IDCT) 16, and a motion compensation (MC) system 18. Memory 20 is used to store the reference frames. The adder combines the error residuals output from IDCT 16 (path 1) with motion compensation results (path 2) to form the final video output 24. Unfortunately, each of these functional components consume a significant amount of computational power, which drives up the cost, and limits the flexibility of digital video systems using MPEG-2 technology. Accordingly, making a highly efficient, cost effective decoder remains one of the main goals of all electronics manufacturers.
One solution for addressing the processing requirements of MPEG-2 decoders is to provide specialized hardware systems that increase computational power. For example, U.S. Pat. No. 5,903,311, issued to Ozcelik et al. on May 11, 1999, which is hereby incorporated by reference, describes a chip that includes specialized circuits for an MPEG-2 decoder. Unfortunately, while overall hardware costs continue to decrease, the costs involved in designing and building specialized hardware such as this increase the expense of the decoder.
A preferred solution therefore is to implement as much functionality as possible in software, which provides significant cost and flexibility advantages over hardware solutions. In particular, software solutions reduce the need for expensive hardware, such as coprocessors, and will allow multiple video functions to run concurrently on a DSPCPU core. However, software applications tend to run too slow to handle occasions when computationally intensive decoding operations are required. Accordingly, a need exists to provide enhanced systems that will provide inexpensive MPEG-2 decoder solutions while maintaining an acceptable level of video quality.